With the progress of CMOS technologies, the development and fabrication of wireless communication LSIs in the GHz band has become possible. The formation of a wireless communication LSI for a Bluetooth system, a wireless LAN, or the like by using a CMOS contributes to the implementation of a lower-cost, lower-power-consumption, and higher-speed system.
In such a system, a continuous-time filter using an analog amplifier such as a transconductance amplifier (Gm amplifier) as an analog filter circuit is used. When such an analog filter circuit is particularly integrated into a CMOS, a transconductance Gm value varies due to variations in the characteristics of a transistor and the time constant of the analog filter circuit greatly varies so that the cutoff frequency of the analog filter circuit or the like shifts on an frequency axis.
Therefore, there has been conventionally proposed a method for performing filter adjustment by using a dummy filter or a dummy oscillator employing the Gm amplifier, which is the component of the analog filter circuit, to adjust the characteristic variations of the analog filter circuit resulting from fabrication variations.
However, in the filter adjustment method described above, such problems as an increase in circuit area, a mismatch between semiconductor elements, and an increase in the number of development steps still remain. To solve these problems, a structure which detects a phase difference between the input/output signals of an analog filter circuit and adjusts an amount of bias for the analog filter circuit is disclosed in, e.g., Patent Document 1.
The conventional filter adjustment circuit based on the detection of the phase difference will be described herein below with reference to FIG. 24. In the drawing, 201 denotes a selector and 202 denotes a Gm-C filter as an analog filter circuit, 203 denotes a multiplier, 204 denotes a filter circuit, 205 denotes a digitization circuit, 206 denotes an up/down counter, 207 denotes a DA conversion circuit for converting a digital amount to an analog amount to generate a bias value.
An operation of the conventional filter adjustment circuit will be described herein below. The description will be given by assuming that the Gm-C filter 202 is a Butterworth Gm-C filter having a fourth-order bandpass characteristic.
In the adjustment of the Gm-C filter 202, the selector 201 is set to input a reference signal to the Gm-C filter 202. As the reference signal, a signal having the center frequency of the Gm-C filter 202 is adopted. Since the phase rotation between the input/output signals at the center frequency is −180° in the fourth-order Butterworth Gm-C filter 202, easy calibration to the center frequency is allowed by adjusting the phase difference between the input/output signals of the Gm-C filter to −180°.
Subsequently, the input/output signals of the Gm-C filter 202 are inputted to the multiplier 203 and a phase error is detected. An output of the multiplier 203 is smoothed by the filter circuit 204 and then converted to digital information by the digitization circuit 205. The up/down counter 206 uses the digital information to count and provide a count value in accordance with a phase lag/lead. An output of the up/down counter 206 is converted to an analog amount by a DA conversion circuit 207 to adjust a bias value for the Gm-C filter 202. When the amount of controlling the transconductance Gm becomes steady, the phase difference between the input/output signals of the Gm-C filter 202 becomes exactly −180°.
Patent Document 1: Japanese Laid-Open Patent Publication No. HEI 10-303699 (pages 1 to 3, FIG. 1).